(Conventional Sensor Device)
FIG. 21 shows a conventional sensor device 300. The sensor device 300 has a sensor region 110 with unit sensors 111 arranged in a matrix with rows and columns which detect a signal in the nature (sensed signal) and convert this signal into an electric signal. The unit sensors 111 are connected to row selection lines 112 and column selection lines 113. A vertical (row) operation circuit 130 supplies a predetermined voltage to one of the row selection lines 112 to select a row of the sensor region 110. The column selection lines 113 are connected to an A/D converting unit 120. The A/D converting unit 120 includes an A/D converter column 122 configured with a plurality of A/D converters arranged in columns. Furthermore, as required, a subtraction amplifier circuit 121 may be inserted between the column selection lines 113 and the A/D converter columns 122. An A/D horizontal (column) operation circuit 150 sequentially selects each column output of the A/D converter columns 122 for transfer to a data output terminal 151 for output. In synchronization with a clock signal supplied to a clock input terminal 141 from a clock supply circuit (not shown), a timing control circuit 140 generates a pulse signal for controlling each of the vertical (row) operation circuit 130 and the horizontal (column) operation circuit 150.
In synchronization with the clock input, a pulse signal is generated at the timing control circuit 140. With a row control signal generated at the vertical (row) operation circuit 130 in synchronization with the pulse signal, one row selection line 112 is activated, and an electric signal of the unit sensor 111 on the target row is taken out to the column selection line 113. Each column signal line is subjected to A/D conversion at the A/D converting unit 120. The A/D converting unit 120 may take a structure in which the subtraction amplifier circuit 121 and the A/D converter column 122 with unit A/D converters arranged in columns. An output signal from the A/D converting unit 120 is taken out from the data output terminal 151 with a control signal generated at the horizontal (column) operation circuit 150.
(Universal Sensor Read Circuit)
The sensor requires a read circuit 160. FIG. 22 shows an universal sensor read circuit 160. A signal from the sensor is represented as a voltage source or current source. For example, a resistive pressure sensor using a resistance change by pressure or the like can detect a change in pressure as a change in voltage occurring at a resistor by letting current flow through the resistor body. Also, a capacitive pressure sensor using a capacitance change by pressure or the like can detect a change in pressure as a change in the amount of charge by a capacitor. The change in the amount of charge can be detected as a change in voltage by using a certain capacitor.
The universal sensor read circuit 160 of FIG. 22 has a sensor 161 (represented as a voltage source) connected to a power supply voltage VDD and one end of a transistor M1. A signal S/H (sample/hold) is supplied to the gate of the transistor M1. A holding capacitor 162 is connected to the other end of the transistor M1. A transistor M4 is connected between the power supply voltage VDD and the holding capacitor 162. A signal RST is supplied to the gate of the transistor M4. The holding capacitor 162 is further connected to the gate of a transistor M2. One end of the transistor M2 is connected to the power supply voltage VDD, and the other end thereof is connected to one end of a transistor M3. A signal SEL is supplied to the gate of the transistor M3, and the other end is connected to a column current source 163. A read voltage VR appears at the other end of the transistor M3.
In FIG. 22, by controlling the gate of the transistor M1 with the signal S/H (sample/hold), the voltage VS of the sensor 161 is sampled and held in the holding capacitor 162. This held voltage is buffered at the transistor M2 forming a source follower, and the gate of the transistor M3 forming a switch is controlled with the row control signal SEL, thereby allowing the voltage to be taken out to the column signal line. The column current source 163 is provided to give a bias current required for the operation of the transistor M2 forming a source follower. In the circuits of FIG. 21, circuits other than the column current source 163 are included in each unit sensor 111 and are arranged in a matrix. On the other hand, the column current source 163 is connected to the column selection line 113 for each column.
In this read circuit 160, a gate-source voltage VGS of the transistor is varied due to variations of a threshold voltage VT of the transistor M2 configuring a source follower, and thus the signal source voltage VS cannot be accurately read. Thus, generally, a reference voltage VREF is first sent from a reference voltage generation circuit (not shown), the voltage VS including the signal is sent next, and a difference between these two voltages is taken, thereby allowing accurate reading of the signal source voltage VS. By using this correlated double sampling, variations of the gate-source voltage VGS can be cancelled. Also, influences of 1/f noise of the transistor can be suppressed. As a matter of course, the voltage VS including the signal may be sent first and then the reference voltage VREF may be sent next.
(Slope A/D Converter)
An output from the sensor read circuit 160 is converted from an analog signal to a digital signal at the A/D converting unit 120. FIG. 23 shows a slope A/D converter 170, which is one of the time domain A/D converters often used in a CMOS image sensor as a typical sensor device, and FIG. 24 shows a relation between the input signal and reference voltage.
The slope A/D converter 170 includes a plurality of unit A/D converters 171 and a ramp wave generator 172 provided in common. Each of the plurality of unit A/D converters 171 includes a comparator 173 and a counter 174. A ramp wave signal line 177 and a clock signal line 176 are provided in common to the plurality of unit A/D converters 171. An output from the ramp wave generator 172 is supplied to the ramp wave signal line 177.
With a ramp wave control signal supplied from VRT to a ramp wave control signal input terminal 179 as a trigger, the ramp wave generator 172 generates a ramp wave 190 with its voltage falling in proportion to time. The counter 174 configuring the unit A/D converter 171 starts counting of clock pulses supplied to the clock signal line 176. The comparator 173 compares an input signal supplied to an input terminal 178 and a reference signal, which is a ramp wave 190 generated at the ramp wave generator 172. When the reference signal is lower than the input signal (Tin), the comparator 173 generates a flag and stops the counter 174. The counter value at that time represents the input signal voltage Vin, and thus this value is taken out at a conversion output terminal 180 as a conversion output, and the counter 174 is reset with a reset signal supplied to a reset terminal 181.
This slope A/D converter has a simple structure, a small differential non-linearity error, compensated monotonicity, and high robustness. Therefore, the slope A/D converter is widely used in a CMOS image sensor.
On the other hand, the slope A/D converter has also many problems. An example of the problems is a tradeoff between conversion speed and resolution. Thus, when a time usable for conversion is TFS, a clock frequency fclk in an A/D converter with a resolution of N bits is represented as follows.fclk=2N/TFS  (1)
It is assumed that the number of frames is NF, the number of vertical pixels is NV, reset read and signal read are performed, and a half of each cycle can be used for A/D conversion. In this case, the following equation holds.TFS=1/(4NFNV)  (2)Thus, the following equation holds.fclk=2N+2NFNV  (3)
When the number of frames is 100, the number of vertical pixels is 2000, and the usable clock frequency is on the order of 2 GHz at maximum, the resolution is on the order of 11 bits, which is on the order of 68 dB in terms of dynamic range.
The accuracy of the A/D converter is determined not only by the clock frequency, and the comparator is also a factor for determining the accuracy of the A/D converter. The noise voltage of the comparator is on the order of 100 μV to 200 μV, which is on the order of 75 dB in terms of dynamic range. Therefore, the dynamic range of the slope A/D converter is 70 dB at the best.
The number of electrons handled by the unit sensor is generally several tens of thousands. Thus, if it is assumed that the number of electrons is thirty thousand and the holding capacitor is 5 fF, the maximum output voltage is on the order of 1 V. The minimum value to a signal to be detected is one electron, and this is equivalent to 30 μV. Therefore, a necessary dynamic range is approximately 90 dB. In the slope A/D converter, it is difficult to achieve a high dynamic range that the pixel intrinsically has. Thus, in one sensor device, a higher dynamic range is tried to be acquired by performing correlated double sampling and, as described above, providing a subtraction amplifier with a variable gain on the order of 0 dB to 20 dB before A/D conversion. However, a large capacitor of 10 pF to 20 pF is often used to suppress noise and, as a result, not only an area increase but also an increase in power consumption is invited.
Therefore, the A/D converter currently used in the sensor device does not achieve a high dynamic range required for the sensor at high speed and with low power consumption.